(*use_dsp="no"*)module multiply (
    //input clk,
    input [23:0]m1_in,
    input [23:0]m2_in,
    output  [47:0]mantissa
);
    //wire [47:0] mantissa;
    assign mantissa=m1_in*m2_in;

/*     always @(posedge clk) begin
            mantissa_o<=mantissa;
    end */
endmodule